Two-modulus prescaler circuit

ABSTRACT

In the dual modulus prescaler circuit, an output terminal of the first multi-input logic gate circuit is connected to a data input terminal of a first D flip-flop circuit; output terminals of the first to (n-2)th D flip-flop circuits are, respectively, connected to data input terminals of the second to (n-1)th D flip-flop circuits; output terminals of the (n-1)th and nth D flip-flop circuits are connected to input terminals of the first multi-input logic gate circuit; the second multi-input logic gate circuit is connected to the output terminal of the (n-1)th D flip-flop circuit and receives a switching signal; and an output terminal of the second multi-input logic gate circuit is connected to a data input terminal of the nth D flip-flop circuit. Moreover, all the aforementioned connections are connections using differential signals.

TECHNICAL FIELD

The present invention relates to a dual modulus prescaler circuitapplicable to frequency synthesizers and the like. Specifically, thepresent invention relates to a dual modulus prescaler circuit which canoperate with small signal amplitude and with reduced power consumption.

BACKGROUND OF THE INVENTION

A “divide-by 4/divide-by 5 divider” switchable between divide-by 4 anddivide-by 5 modes, which is a basis for a dual modulus prescaler usedfor a pulse swallow type PLL synthesizer, is composed of a circuit asshown in FIG. 1. In FIG. 1, reference numerals 11 to 13 denote Dflip-flop circuits (DFF circuits), and reference numerals 14 and 15denote NOR circuits. This circuit is configured to switch betweendivide-by 4 and divide-by 5 modes by means of a polarity of an inputsignal of a terminal M.

FIG. 2 is a timing chart showing an operation of the “divide-by4/divide-by 5 divider”. As shown in FIG. 2, in the “divide-by4/divide-by 5 divider”, when an input of the terminal M is H1, an inputD of the DFF3 remains unchanged, and the input signal isfrequency-divided by four with the DFF1 and DFF2. On the contrary, whenthe input of the terminal M is Low, the DFF3 operates, and the inputsignal is frequency-divided by five.

Further, by adding a frequency divider to the output of the circuit, adual modulus prescaler circuit switchable between divide-by 2n anddivide-by 2n+1 modes can be configured. FIG. 3 is a block diagram of a“divide-by 32/divide-by 33 divider” using the “divide-by 4/divide-by 5divider”. Reference numerals 11 to 13 denote D flip-flop circuits (DFFcircuits); 14 and 15. NOR circuits; 16, an OR circuit; and 21 to 23, Tflip-flop circuits (TFF circuits).

In the circuit of FIG. 3, each of the DFF1, DFF2, and DFF3 constitutingthe “divide-by 4/divide-by 5 divider” is required to operate at afrequency of an input signal. The TFF1, TFF2, and TFF3 which receivedivided signals operate at a lower frequency as they get closer to thelast stage.

Therefore, in order to reduce the power consumption of the dual modulusprescaler, it is important to reduce the power consumption of the“divide-by 4/divide-by 5 divider”. Generally, prescalers requirehigh-speed operation, and so bipolar processes are often used. However,CMOS prescalers have been developed along with achieving higher speedCMOS processes in recent years.

In the case of CMOS processes, it is possible to conceive a DFF circuitusing a current mode logic circuit as shown in FIG. 4, which can beexpected to offer faster performance than that using normal CMOS gates.The circuit of FIG. 4 includes a master FF and a slave FF. The master FFis composed of transistors M1 to M6 and R1 and R2, and the slave FF iscomposed of M8 to M13, R3, and R4. I-1 and I-2 of FIG. 4 denote currentsources.

The transistors M5 and M6 and the transistors M12 and M13 are turned onand off by a clock inputted as a differential signal to switch currentpaths. When CN is Hi and CP is Low, the current path is through the M5side in the master FF. At this time, if a gate voltage IN of M1 ishigher than a gate voltage IP of M2, current flows through R1, and Lowis read. If IN is lower than IP, current flows through R2, and H1 isread. Simultaneously, the current path Is through the M13 side in theslave FF, and an output is held by M10 and M11.

When CN is Low and CP is Hi, the current path is through the M6 side inthe master FF, and data is held by M3 and M4. The current path isthrough the M12 side in the slave FF, and data is outputted through M8and M9. This circuit operates as a DFF circuit according to theaforementioned operations.

The NOR circuit used in the “divide-by 4/divide-by 5 divider” can beeasily implemented only by replacing the transistor M1 for data input inthe DFF circuit of FIG. 4 with transistors M1A and M1B connected to eachother in parallel as shown in FIG. 5. Signals and the like in FIG. 5 arethe same as those in FIG. 4.

In the DFF circuit with a NOR gate shown in FIG. 5, in reading data whenCP is Low, if any one of a gate voltage A of M1A and a gate voltage B ofM1B or both thereof are higher than a gate voltage VR of M2, currentflows through R1, and Low is read. When both of A and B are lower thanVR, current flows through R2, and Hi is read. Therefore, this circuitoperates as a DFF circuit with a NOR gate.

The DFF circuit with a NOR gate shown in FIG. 5 requires a thresholdvoltage VR for judging whether data is Low or Hi since single-phase datais inputted. Power supply voltage necessary for operating this circuitrequires being a voltage value obtained by adding signal amplitude tooperating voltages of individual transistors. The DFF circuit with a NORgate of FIG. 5 requires a total voltage of a voltage for operating threetransistors and signal amplitude.

Larger signal amplitude provides larger operating margins but requireslarger power supply voltage. The DFF circuit with a NOR gate of FIG. 5requires larger signal amplitude to ensure a DC bias operating marginsince single-phase data is inputted. Therefore, it is difficult toreduce the power supply voltage.

SUMMARY OF THE INVENTION

The present invention according to the application was made to solve theaforementioned problem. Specifically, an aspect of the present inventionaccording to claim 1 is a dual modulus prescaler circuit for dividing aninputted clock signal to obtain a divide ratio which is selected by aswitching signal from a combination of predetermined divide ratios. Thedual modulus prescaler circuit includes: n D flip-flop circuits, n beinga natural number not less than three; a first multi-input logic gatecircuit including at least two input terminals; and a second multi-inputlogic gate circuit including at least two input terminals. An outputterminal of the first multi-input logic gate circuit is connected to adata input terminal of the first D flip-flop circuit; output terminalsof the first to (n-2)th D flip-flop circuits are connected to data inputterminals of the second to (n-1)th D flip-flop circuits; outputterminals of the (n-1)th and nth D flip-flop circuits are connected toinput terminals of the first multi-input logic gate circuit; the secondmulti-input logic gate circuit is connected to the output terminal ofthe (n-1)th D flip-flop circuit and receives the switching signal, andan output terminal of the second multi-input logic gate circuit isconnected to the data input terminal of the nth D flip-flop circuit.Moreover, all the aforementioned connections are connections usingdifferential signals.

Another aspect of the present invention according to claim 2 is the dualmodulus prescaler circuit according to claim 1, in which a multi-inputlogic gate circuit is used for each of the first and second multi-inputlogic gate circuits, the multi-input logic gate circuit including acurrent source, first and second resistors each of which has an endconnected to a power supply, m transistors connected in parallel, whosesources are connected to an output end of the current source and whosedrains are connected to the other end of the first resistor, and furtherm transistors connected in series, whose sources and drains areconnected between the output end of the current source and the other endof the second resistor. Herein, m is a natural number not less than two.Moreover, m differential input data are applied between gates of thetransistors connected in parallel and gates of the transistors connectedin series, and a differential signal is obtained as an output of themulti-input logic gate circuit at the other ends of the first and secondresistors.

A still another aspect of the present invention according to claim 3 isthe dual modulus prescaler according to claim 1, in which a D flip-flopcircuit with a logic gate circuit is used for each of combinations ofthe first multi-input logic gate circuit and the first D flip-flopcircuit and of the second multi-input logic gate circuit and the nth Dflip-flop circuit, the logic gate circuit including: first and secondcurrent sources; first and second transistors whose sources areconnected to an output end of the first current source; third and fourthtransistors whose sources are connected to an output end of the secondcurrent source; fifth, sixth, and seventh transistors whose sources areconnected to a drain of the first transistor; an eighth transistor whosesource is connected to a drain of the seventh transistor; ninth andtenth transistors whose sources are connected to a drain of the secondtransistor; eleventh and twelfth transistors whose sources are connectedto a drain of the third transistor; thirteenth and fourteenthtransistors whose sources are connected to a drain of the fourthtransistor; a first resistor whose terminal is connected to a powersupply and whose other terminal is connected to drains of the fifth,sixth, and ninth transistors and to gates of the tenth and eleventhtransistors; a second resistor whose terminal is connected to the powersupply and whose other terminal is connected to drains of the eighth andtenth transistors and to gates of the ninth and twelfth transistors; athird resistor whose terminal is connected to the power supply and whoseother terminal is connected to drains of the eleventh and thirteenthtransistors and to a gate of the fourteenth transistor; and a fourthresistor whose terminal is connected to the power supply and whose otherterminal is connected to drains of the twelfth and fourteenthtransistors and to a gate of the thirteenth transistor. Moreover,differential clock signals are applied between gates of the first andfourth transistors and between gates of the second and thirdtransistors; a first differential data is applied between gates of thefifth and eighth transistors; and a second differential data is appliedbetween gates of the sixth and seventh transistors.

Still another aspect of the present invention according to claim 4 isthe dual modulus prescaler circuit according to claim 3, in which, inthe D flip-flop circuit with a logic gate circuit, the current sourcesare eliminated, and the sources of the first, second, third, and fourthtransistors are connected to the ground.

In the present invention, as described above, the DFF circuit with a NORgate is configured to receive differential inputs, so that the signalamplitude can be reduced. The use of differential signals allows thesignal amplitude to be reduced to half, thus achieving reduced powersupply voltage. Therefore, there are a method for constituting the DFFcircuit with a NOR gate by use of a differential input/differentialoutput NOR/OR circuit and a differential DFF circuit and a method forusing a differential input DFF circuit with a NOR gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a configuration of a conventional “divide-by4/divide-by 5 divider”.

FIG. 2 is a view showing a timing chart of the conventional “divide-by4/divide-by 5 dividers”.

FIG. 3 is a view showing a configuration of a conventional “divide-by32/divide-by 33 divider”.

FIG. 4 is a view showing a configuration of a conventional DFF circuit.

FIG. 5 is a view showing a configuration of a conventional DFF circuitwith a NOR gate.

FIG. 6 is a view showing a configuration of a circuit according to afirst embodiment.

FIG. 7 is a view showing a configuration of a differential input/outputNOR circuit according to the first embodiment.

FIG. 8 is a view showing a configuration of a DFF circuit with a NORgate according to a second embodiment.

DETAIL DESCRIPTION OF THE INVENTION

FIG. 6 is a view showing a first embodiment of the present invention.This embodiment corresponds to an aspect of the present inventionaccording to claim 1. In the drawing, reference numerals 1 to 3 denoteDFF circuits, and 4 and 5 denote NOR circuits. The circuit of FIG. 6 isconfigured so that differential signals are inputted to/outputted fromall the DFF circuits (D flip-flop circuits) and NOR circuits(multi-input logical gate circuits). An example of the differentialinput/output NOR circuit is shown in FIG. 7. This circuit corresponds toa NOR circuit defined by another aspect of the present inventionaccording to claim 2.

The circuit of FIG. 7 is a NOR circuit operated in a current mode inorder to ensure high speed performance. In FIG. 7, R1 and R2 denoteresistors: M1 to M4, transistors; I-1, a current source; AP, an inputsignal; and YP, an output signal. When the terminals AP and BP in thecircuit of FIG. 7 are Hi, AN and BN are Low. At this time, current flowsthrough R1 but does not flow through R2. Accordingly, YP is Low, and YNis Hi. When AP is Hi and BP is Low or when YP is Low and BP is Hi,current flows through R1. Accordingly, YP is Low, and YN is Hi. In otherwords, YP acts as the NOR to AP and BP. Herein, the aforementionedcircuit of FIG. 4 is used for each of the DFF circuits.

The circuit of FIG. 4 includes a master FF and a slave FF. The master FFis composed of transistors M1 to M6 and R1 and R2, and the slave FF iscomposed of M8 to M13 and R3 and R4. The transistors M5 and M6 and thetransistors M12 and M13 are turned on and off by a clock inputted as adifferential signal to switch current paths.

When CN is Hi and CP is Low, the current path is through the M5 side inthe master FF. At this time, if a gate voltage IN of M1 is higher than agate voltage IP of M2, current flows through R1, and Low is read. If INis lower than IP, current flows through R2, and Hi is read.Simultaneously, the current path in the slave FF is through the M13side, and the output is held by M10 and M11.

When CN is Low and CP is Hi, the current path is through the M6 side inthe master FF, and data is held by M3 and M4. In the slave FF, thecurrent path is through the M12 side, and data is outputted through M8and M9. This circuit operates as a DFF circuit according to theaforementioned operations. A fully differential “divide-by 4/divide-by 5divider” can be implemented by using the circuit of FIG. 7 for each NORcircuit and using the circuit of FIG. 4 for each DFF circuit.

FIG. 8 is a view showing a second embodiment of the present invention,corresponding to still another aspect of the invention according toclaim 3. The circuit of FIG. 8 is a circuit in which the transistor M2of the DFF circuit with a NOR gate shown in FIG. 5 is replaced withtransistors M2A and M2B which are connected in series. In the circuit ofFIG. 8, differential signals are applied between AP and AN and betweenBP and BN.

In reading data when CP is Low, only in the case where AP and BP areLow, AN and BN are Hi, and current flows through R2. Accordingly, Hi isread. In other cases, current flows through any one or both of M1A andM1B, and any one or both of M2A and M2B are turned off. Accordingly,current flows through R1, and Low is read.

Therefore, the circuit of FIG. 8 operates as the DFF circuit with a NORgate. It is possible to implement the fully differential “divide-by4/divide-by 5 divider” by applying the DFF circuit with a NOR gate ofFIG. 8 to each of combinations of NOR1 and DFF1 and of NOR2 and DFF 3 inFIG. 6 and applying the DFF circuit of FIG. 4 to DFF2. Moreover, the DFFcircuit with a NOR gate of FIG. 8 and the DFF circuit of FIG. 4 canoperate even when the current sources are omitted since the clocksignals thereof are differential. Accordingly, the power supply voltagecan be further lowered by omitting the current sources.

Industrial Applicability

According to the present invention, all the circuits constituting thedual modulus prescaler are designed to be differential input and/ordifferential output circuits. Accordingly, compared to conventionalcircuits operating margins for signal amplitude and a signal directcurrent level can be increased, so that the dual modulus prescaler canoperate with smaller signal amplitude. This offers advantages ofreducing power supply voltage and power consumption.

1. A dual modulus prescaler circuit for dividing an inputted clocksignal to obtain a divide ratio which is selected by a switching signalfrom a combination of predetermined divide ratios, the dual modulusprescaler circuit comprising: n D flip-flop circuits, n being a naturalnumber not less than three; a first multi-input logic gate circuitincluding at least two inputs: and a second multi-input logic gatecircuit including at least two inputs, wherein an output terminal of thefirst multi-input logic gate circuit is connected to a data inputterminal of the first D flip-flop circuit, output terminals of the firstto (n-2)th D flip-flop circuits are connected to data input terminals ofthe second to (n-1)th D flip-flop circuits, output terminals of the(n-1)th and nth D flip-flop circuits are connected to input terminals ofthe first multi-input logic gate circuit, the second multi-input logicgate circuit is connected to the output terminal of the (n-1)th Dflip-flop circuit and includes a terminal to which the switching signalis inputted, and an output terminal of the second multi-input logic gatecircuit is connected to a data input terminal of the nth D flip-flopcircuit, and wherein all the connections are connections usingdifferential signals.
 2. The dual modulus prescaler circuit according toclaim 1, wherein a multi-input logic gate circuit is used for each ofthe first and second multi-input logic gate circuits, the multi-inputlogic gate circuit including a current source, first and secondresistors each of which has an end connected to a power supply, mtransistors connected in parallel, m being a natural number not lessthan two, whose sources are connected to an output end of the currentsource and whose drains are connected to the other end of the firstresistor and further m transistors connected in series, whose sourcesand drains are connected between the output end of the current sourceand the other end of the second resistor, wherein m differential inputdata are applied between gates of the transistors connected in paralleland gates of the transistors connected in series, and wherein adifferential signal is obtained as an output of the multi-input logicgate circuit at the other ends of the first and second resistors.
 3. Thedual modulus prescaler according to claim 1, wherein a D flip-flopcircuit with a logic gate circuit is used for each of combinations ofthe first multi-input logic gate circuit and the first D flip-flopcircuit and of the second multi-input logic gate circuit and the nth Dflip-flop circuit, the logic gate circuit including: first and secondcurrent sources; first and second transistors whose sources areconnected to an output end of the first current source; third and fourthtransistors whose sources are connected to an output end of the secondcurrent source; fifth, sixth, and seventh transistors whose sources areconnected to a drain of the first transistor; an eighth transistor whosesource is connected to a drain of the seventh transistor; ninth andtenth transistors whose sources are connected to a drain of the secondtransistor; eleventh and twelfth transistors whose sources are connectedto a drain of the third transistor; thirteenth and fourteenthtransistors whose sources are connected to a drain of the fourthtransistor; a first resistor whose terminal is connected to a powersupply and whose other terminal is connected to drains of the fifth,sixth, and ninth transistors and to gates of the tenth and eleventhtransistors; a second resistor whose terminal is connected to the powersupply and whose other terminal is connected to drains of the eighth andtenth transistors and to gates of the ninth and twelfth transistors; athird resistor whose terminal is connected to the power supply and whoseother terminal is connected to drains of the eleventh and thirteenthtransistors and to a gate of the fourteenth transistor; and a fourthresistor whose terminal is connected to the power supply and whose otherterminal is connected to drains of the twelfth and fourteenthtransistors and to a gate of the thirteenth transistor, and whereindifferential clock signals are applied between gates of the first andfourth transistors and between gates of the second and thirdtransistors; a first differential data is applied between gates of thefifth and eighth transistors; and a second differential data is appliedbetween gates of the sixth and seventh transistors.
 4. The dual modulusprescaler circuit according to claim 3, wherein, in the D flip-flopcircuit with a logic gate circuit, the current sources are eliminated,and the sources of the first, second, third, and fourth transistors areconnected to the ground.